In order to perform burst-mode transition in the prior art, use is made of a clock recovery circuit for generating a clock that is accurately synchronized to data. A clock recovery circuit for such burst-mode transmission according to the prior art will be described with reference to FIG. 6, which is a block diagram illustrating the conventional clock recovery circuit.
The clock recovery circuit depicted in FIG. 6 is disclosed in Electronics Letters, Nov. 5, 1992, Vol.28, No 23, pp. 2127-2129. As shown in FIG. 6, the clock recovery circuit comprises a delay circuit (Delay) 305 to which data 301 is input; a gate-input controlled oscillator (GVCO) 307 to which the data 301 is input; an inverter 315 for inverting the data 301, which is input thereto; a gate-input controlled oscillator (GVCO) 309 to which the inverted data output by the inverter 315 is input; a multiplexing circuit (MUX) 308 for combining the outputs of the gate-input controlled oscillators 307, 309 and outputting the resulting signal as an extracted clock; a data-type flip-flop (referred as a "D-F/F" below) 306 having a data terminal to which the extracted clock 303 output by the multiplexing circuit 308 is input, whereby the delayed data 301 output by the delay circuit 305 is latched and output as reproduced data 302; a phase detecting circuit (PD) 311 to which a reference clock 304 is input; and a loop filter (LF)/charge pump (CP) 312 to which a signal output by the phase detecting circuit 311 is input and from which an output signal is delivered to the gate-input controlled oscillators 307,309 and to a gate-input controlled oscillator (GVCO)310, the latter delivering its output signal to the phase detecting circuit 311 based upon the signal output by the loop filter/charge pump 312.
The phase detecting circuit 311, loop filter/charge pump 312 and gate-input controlled oscillator 310 in this clock recovery circuit construct a phase-locked loop (referred to as a "PLL" below).
Thus, the clock recovery circuit shown in FIG. 6 is constituted by a PLL the basic components of which are the single loop filter/charge pump 312, the single phase detecting circuit 311, the single multiplexing circuit 308, the single delay circuit 305, the single D-F/F 306 serving as a latch circuit, and the three gate-input controlled oscillators 307, 309,310.
The operation of the conventional clock recovery circuit shown in FIG. 6 will now be described.
In terms of the connections, an ordinary PLL is constructed by the loop filter/charge pump 312, phase detecting circuit 311 and one gate-input controlled oscillator 310. The reference clock 304 is input to the phase detecting circuit 311, which becomes synchronized to the reference clock 304 and delivers its output to the loop filter/charge pump 312. The output signal from the loop filter/charge pump 312 enters the gate-input controlled oscillators 307, 309 and 310. Accordingly, the outputs of the gate-input controlled oscillators 307 and 309 are synchronized to the reference clock 304 at all times.
The timings of the various signals associated with the conventional clock recovery circuit shown in FIG. 6 will be described with reference to FIG. 7, which is a timing chart illustrating these signals.
As shown in FIG. 7, the gate-input controlled oscillator 307 outputs a clock A in conformity with the rising edge of the data 301 and the gate-input controlled oscillator 309 outputs a clock B in conformity with the falling edge of the data 301. The two clocks A and B are multiplexed by the multiplexing circuit 308, whereby the extracted clock 303 is produced. Further, owing to the input of the extracted clock 303 to the its data terminal, the D-F/F 306 latches the data 301 that has passed through the delay circuit 305 and generates the reproduced data 302. As a result, the extracted clock 303 synchronized to the data and the reproduced data 302 can be obtained with the clock recovery circuit according to the prior art illustrated in FIG. 6.
Further, a clock recovery circuit employing a similar technique using the data 301 instead of the reference clock 304 has been disclosed in the 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 122-123.